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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Tipsuwanporn V. | |
dc.contributor.author | Tirasesth K. | |
dc.contributor.author | Sattho U. | |
dc.contributor.author | Witheephanich K. | |
dc.contributor.author | Chuenarom S. | |
dc.date.accessioned | 2021-04-05T04:33:19Z | - |
dc.date.available | 2021-04-05T04:33:19Z | - |
dc.date.issued | 2000 | |
dc.identifier.other | 2-s2.0-2342557232 | |
dc.identifier.uri | https://ir.swu.ac.th/jspui/handle/123456789/15275 | - |
dc.identifier.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-2342557232&partnerID=40&md5=006fa0273d600b64fa1b7d7de442c866 | |
dc.description.abstract | In this paper voltage-to-frequency conversion (VFC) circuit with Binary Rate Multipliers (BRM) output is presented. We first analyze spectrum value and percentage of Binary Bit Rate (BBR) power then reject the repeated power values, and select only one BBR signal to construct BRM by linear combination. A VFC design with 1 to 5 volts (Vin) and ±2.5 volts (Vout) can generate BRM pattern (0 Hz - 39.0625 kHz) in sine, triangular, saw-tooth and square waveform. The average value of VFC output signal is fedback to input of the VFC in order to stabilize pattern for BRM transmission. The output patterns and frequencies can be controlled either independently or simultaneously. | |
dc.subject | DC motors | |
dc.subject | Modulation | |
dc.subject | Multiplying circuits | |
dc.subject | Oscillations | |
dc.subject | Speed control | |
dc.subject | Voltage control | |
dc.subject | Binary bit rate (BBR) | |
dc.subject | Binary rate multipliers (BRM) | |
dc.subject | Voltage to frequency conversion (VFC) | |
dc.subject | Electric converters | |
dc.title | Independent BRM multi patterns with VFC | |
dc.type | Conference Paper | |
dc.rights.holder | Scopus | |
dc.identifier.bibliograpycitation | IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings. Vol , No. (2000), p.622-625 | |
Appears in Collections: | Scopus 1983-2021 |
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