Please use this identifier to cite or link to this item: https://ir.swu.ac.th/jspui/handle/123456789/15275
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dc.contributor.authorTipsuwanporn V.
dc.contributor.authorTirasesth K.
dc.contributor.authorSattho U.
dc.contributor.authorWitheephanich K.
dc.contributor.authorChuenarom S.
dc.date.accessioned2021-04-05T04:33:19Z-
dc.date.available2021-04-05T04:33:19Z-
dc.date.issued2000
dc.identifier.other2-s2.0-2342557232
dc.identifier.urihttps://ir.swu.ac.th/jspui/handle/123456789/15275-
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-2342557232&partnerID=40&md5=006fa0273d600b64fa1b7d7de442c866
dc.description.abstractIn this paper voltage-to-frequency conversion (VFC) circuit with Binary Rate Multipliers (BRM) output is presented. We first analyze spectrum value and percentage of Binary Bit Rate (BBR) power then reject the repeated power values, and select only one BBR signal to construct BRM by linear combination. A VFC design with 1 to 5 volts (Vin) and ±2.5 volts (Vout) can generate BRM pattern (0 Hz - 39.0625 kHz) in sine, triangular, saw-tooth and square waveform. The average value of VFC output signal is fedback to input of the VFC in order to stabilize pattern for BRM transmission. The output patterns and frequencies can be controlled either independently or simultaneously.
dc.subjectDC motors
dc.subjectModulation
dc.subjectMultiplying circuits
dc.subjectOscillations
dc.subjectSpeed control
dc.subjectVoltage control
dc.subjectBinary bit rate (BBR)
dc.subjectBinary rate multipliers (BRM)
dc.subjectVoltage to frequency conversion (VFC)
dc.subjectElectric converters
dc.titleIndependent BRM multi patterns with VFC
dc.typeConference Paper
dc.rights.holderScopus
dc.identifier.bibliograpycitationIEEE Asia-Pacific Conference on Circuits and Systems - Proceedings. Vol , No. (2000), p.622-625
Appears in Collections:Scopus 1983-2021

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